Non-volatile memory cells are widely used because they can store data even when the power supply is cut off. Each memory cell is composed of a MOS transistor and a silicon nitride layer. Since the silicon nitride layer has a high density, hot electrons tunnel through the MOS transistor to become trapped in the silicon nitride layer, thus achieving information storage. During programming, electrical charge is transferred from the substrate to the silicon nitride layer located in an oxide-nitride-oxide (ONO) layer.
In the conventional fabrication in the step of defining tunnel regions, a hard mask is formed to cover the tunnel region. However, it leads to nitride residue being formed if the hard mask covers outside the tunnel region and results in non-uniformity of sequentially performed doping process; on the other hand, it leads to underlying silicon pitting by the following etching process if the hard mask covers only the tunnel region. And thus performances of the memory cells are limited and influenced by the conventional manufacturing process.
Therefore, it is necessary to provide an advanced method for fabricating an SONOS memory cell to obviate the drawbacks and problems encountered from the prior art.